Senior Leadership Role in ASIC Digital IP Design
We are seeking a seasoned professional to lead our multi-site engineering team in the development of advanced IP cores. This position offers a unique opportunity to drive strategic direction, optimize processes, and collaborate with experienced engineers.
* Experience: 18+ years in VLSI design, preferably with extensive knowledge of ASIC methodologies.
* Versatility: Hands-on experience with Verilog/System Verlog is essential for this role.
This senior leadership position provides competitive benefits and emphasizes a culture of collaboration and continuous learning.
The ideal candidate will thrive in an environment that values innovation, efficiency, and teamwork.
This is an exciting opportunity for professionals who seek challenges and growth opportunities within their careers.