Job Description
A senior digital verification engineer is required to develop and implement testbenches for complex digital designs using SystemVerilog - UVM.
This position involves developing right from scratch UVC components for new verification environments, defining and writing functional coverage models, debugging failing test cases, and participating in reviews to ensure the test bench meets quality and is complete.
Key Skills and Qualifications
* At least 8 years of experience in verification working with Verilog and/or SystemVerilog;
* 5 years of experience on IP/block level Test-bench bring up on SV UVM based platform;
* The ability to understand complex design specifications, derive features and test bench architectures from concept;
* Familiarity with CAD/EDA tools for Design and Simulation;
* Working knowledge in scripting languages for verification environments (Python, Perl, TCL would be preferred);
* Strong background in Digital Logic Design and Verification
What We Offer
We provide ongoing training and support, flexible working conditions, sabbaticals, health care, private insurance offers and pension plans as well as a compensation package which includes a generous base and bonus scheme.
Requirements
Visa sponsorship can be provided but relocation is a must and remote work is NOT an option for the role. EU Nationals can work without sponsorship.