Digital Physical Designer
Key Skills
1. Ability to set up and run Synthesis, Place and Route and STA.
2. Experience with the Cadence implementation tool-chain (Genus, Innovus, Tempus).
3. From-scratch setup of tool scripts and flows, using previous experience and foundry documentation.
4. Experience in sub 28nm digital implementation.
5. Ability to work closely with design team to develop constraints and resolve issues.
6. Insertion of DFT for scan - including OCC.
7. Clock-tree synthesis and associated analysis of clock-tree issues, feeding back suggestions and improvements to design team.
8. Floorplanning and integration of third-party macros, including high-speed interfaces, SRAM and ROM.
9. Chip-level pad-to-pad timing analysis.
Desirable
1. Generation of library files (.lib, .ccs) for custom cells.
2. Working in a mixed analogue/digital environment – analogue-on-top schematics.
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