About Cadence Design Systems Inc.
We seek to hire and develop leaders and innovators who can make a significant impact on the technology world.
Principal Physical Design Engineer (PNR / Physical Verification / STA / EMIR)
This role will involve working on a variety of challenging design projects, including low power and high speed designs. Additionally, the candidate will have the opportunity to participate in or lead the development of next generation PHY IP physical design methodologies and flows. The candidate will work closely with our RTL design team and Analog Team to ensure successful tapeouts.
Main Job Tasks and Responsibilities:
* Participating in or leading the development of next-generation physical design methodologies and flows for advanced technology nodes.
* Performing physical design implementation tasks, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
Position Requirements:
* Bachelor's degree or above in EE/CS/IT, with 10+ years of work experience.
* Extensive knowledge of design rules for N7/N5 and below process technologies.
* Familiarity with scripting languages and their use in methodology.
* Ability to fix physical design violations, including DRC, DFM, LVS, ANT, ERC etc.
* Deep experience with static timing analysis.
* Ability to learn quickly.
* High level of communication and teamwork skills.
* Carefulness, responsibility, and persistence.
We're Working on Something Meaningful.
We welcome applications from candidates with disabilities and those from equity-seeking groups. If you require accommodations during the application and interview process, please let us know.