Job Title:
Cad Physical Design Product Engineer
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About the Role:
The Global Cad Team is responsible for delivering RTL-to-GDSII solutions for cutting-edge semiconductor products.
* We are seeking an experienced Cad Product Engineer with a strong background in Physical Design, automation, and specification development.
Key Responsibilities:
* Technology enablement and reference flow development for advanced tech nodes (below 4nm).
* Collaborate with EDA vendors to enable production-ready toolsets and enhance PPA metrics across various design blocks.
* Partner with core and SoC design teams to define priorities and timelines for the development of solutions targeting advanced multi-die implementation and advanced process nodes, also to support these teams through the flow execution.
* Validate developed flows across the full PD stack: synthesis, place & route, timing signoff, and physical verification.
* Engage with Vendors, PD teams and IP teams to resolve issues arising in tech enablement and PD execution.
Requirements:
* Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
* OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
* OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Preferred Qualifications:
* Bachelor's degree in electrical/computer engineering master's degree is a plus.
* Solid understanding of CMOS circuit design & exposure to VLSI concepts.
* Minimum of 6 years Physical Design work experience with below requirement.
* Experienced in Floorplanning lower technologies 4nm and below.
* Place & Route tool experience on Synopsys FC and/or Cadence Innovus.
* Placement (experienced in mitigating legalization, secPG routing and congestion challenges), CTS (Skew balancing).
* Very good understanding on DRC debugging.
* Signoff Physical verification using calibre.
* Understanding the usage tech lefs & std cell libraries, exposure to DRC rules of advanced tech nodes (below 7nm), std cell architectures & associated challenges.
* Good exposure to PD implementation of PPA critical Cores, routing intensive designs and making right PPA trade-off decisions.
* Strong problem-solving skills with excellent analytical and debugging skills.
* Experience in Timing closure with Primetime/Tempus, Static IR analysis and GDS export & Physical verification with Calibre.
* Deep knowledge on scripting and software languages including PERL/TCL/Python, Linux/Unix shell.
* Excellent communication, planning, and teamwork skills.
* Experience of working as part of a larger team and working towards project milestones and deadlines.
What We Offer:
* Salary, stock and performance related bonus.
* Maternity/Paternity Leave.
* Employee stock purchase scheme.
* Matching pension scheme.
* Education Assistance.
* Relocation and immigration support (if needed).
* Life, Medical, Income and Travel Insurance.
* Subsidised memberships for physical and mental well-being.
* Bicycle purchase scheme.
* Employee run clubs, including, running, football, chess, badminton + many more.