Salary: Senior Staff Verification Engineer
Job Description:
We are seeking an experienced Senior Staff Verification Engineer to join our team. The role requires collaboration with design, firmware, and hardware emulation teams to ensure the verification of proprietary power devices.
Key Responsibilities:
* Develop verification environments for block, subsystem, and SoC level designs.
* Create UVM-SV Scoreboards for self-checking regressions.
* Design and implement Functional Coverage items like Covergroups and Corverpoints.
* Develop SystemVerilog Assertions for simulation environments.
* Define and manage Verification Plans using Cadence vManager tools.
* Create Automated Regression Environments.
Required Skills and Qualifications:
The ideal candidate will have a PhD or post-graduate degree in Electronic Engineering or similar. They should have at least 10 years of relevant engineering experience, including full-product verification flows and experience with mixed-signal ICs.
Benefits:
This is an excellent opportunity for an experienced Verification Engineer to work on challenging projects and develop their skills further.
Others:
The successful candidate will be working closely with cross-functional teams, including analog designers, digital designers, systems architecture, firmware, applications, and test engineering.
Key qualifications include knowledge of protocol interfaces for spec compliance, strong interpersonal and communication skills, and the ability to work with automated regression environments.