Senior Verification Expert Wanted
We are seeking a skilled Senior Verification Engineer to join our team and contribute to the development of advanced testbenches for video and computer vision IP blocks.
* The ideal candidate will have a Bachelor's or Master's degree and over 5 years of experience in design verification.
Candidates should possess strong expertise in System Verilog and UVM, as well as proficiency in scripting languages like Python or Perl.
This role provides an opportunity to work cross-functionally within a dynamic environment, fostering growth and collaboration.
Fundamental Requirements:
* Bachelor's or Master's degree in Computer Science, Electrical Engineering, or related field
* Over 5 years of experience in design verification
* Proficiency in System Verilog and UVM
* Scripting skills in languages like Python or Perl
About the Opportunity:
This senior role offers a unique chance to drive innovation and excellence in our cutting-edge IP blocks. As a key member of our team, you will collaborate with experts from diverse backgrounds to deliver high-quality solutions.