Senior Design Verification Engineer Opportunity
We are seeking a skilled Senior Design Verification Engineer to join our team.
This role involves developing verification methodologies and ensuring quality deliverables. The ideal candidate should have over 3 years of relevant experience in UVM and System Verilog, along with a degree in Engineering.
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Key Responsibilities:
* Develop and implement verification strategies for complex digital designs
* Collaborate with cross-functional teams to ensure timely delivery of high-quality results
* Maintain and improve existing verification infrastructure and tools
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Requirements:
* Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related field
* Proven expertise in UVM and System Verilog
* At least 3 years of experience in design verification
* Strong problem-solving skills and ability to work independently
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Benefits:
* Full-time employment opportunity
* Chance to work on innovative projects and technologies
* Ongoing training and development opportunities