About Cadence
Cadence is a pioneering leader in electronic design, applying 30 years of software expertise to deliver software, hardware and IP that turn design concepts into reality.
Job Title
Design Engineering Architect
Location
Cork/Dublin, Ireland
Reports To
Design Engineering Director
Job Overview
Cadence Silicon Solutions Group (SSG) develops leading‑edge Intellectual Property (IP) for a variety of high‑tech markets. Our IP solutions enable customers to tackle IP‑to‑SoC development within a system context, reducing time to volume and supporting product differentiation. The Design Engineering Architect will be based in Cork as part of an experienced Controller IP team with sites in Europe, the US and India.
The Cadence IP Vision is to deliver industry‑leading IP solutions that empower our customers across fast‑moving application spaces.
Job Responsibilities
Technical leadership of complex IP such as UCIe, Ethernet, HBM and PCIe.
Collaborate with system architects and product managers to define architecture and specifications on standards such as UCIe, considering data rate, power consumption, and compatibility with industry standards.
Hands‑on leadership of RTL development from micro‑architecture definition to IP sign‑off for general release.
Contribute to planning of activities and milestones for the digital development teams.
Lead cross‑functional technical meetings with Analog and Software counterparts.
Support customer pre‑sales and post‑sales meetings.
Develop, maintain and improve processes and procedures for efficient product execution, IP quality and industry best practices.
Participate in technical review meetings and checklist reviews as part of ISO‑9001.
Represent Cadence in standards body working groups such as IEEE, PCI‑SIG, JEDEC and UCIe.
Present at industry conferences such as IEEE DAC.
Job Qualifications
Degree in Electrical/Electronic Engineering, microelectronics or a related discipline.
15‑20 years’ experience in the microelectronics industry.
Expert proficiency in Verilog/SystemVerilog RTL design.
Expertise in front‑end design tools covering lint, synthesis, CDC/RDC analysis.
Experience with SoC architecture and development.
Experience in technical team leadership.
Excellent oral and written English communication skills.
Self‑motivated with strong planning, interpersonal skills and the ability to communicate complex concepts clearly.
Additional Skills / Preferences
Experience with metric‑driven verification (MDV) and UVM.
Experience with industry standard protocols such as AXI, CHI‑C2C and CXS.B.
Experience with quality processes such as ISO‑9001 and ISO‑26262.
Travel
Less than 10%
EEO Statement
Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
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