We are seeking a highly skilled Digital Design Engineer to join our team in the development of complex mixed-signal ICs. This is an exciting opportunity for a talented individual to work on cutting-edge projects and contribute to the advancement of next-generation computing experiences.
Job Description
We are looking for a motivated and experienced Digital Design Engineer to design and implement complex clock and data recovery algorithms, adaptive digitally assisted control loops, and advanced DSP designs to achieve power-efficient channel equalization solutions. The successful candidate will work closely with an experienced mixed-signal design team to deliver world-class SerDes solutions.
Key Responsibilities
* RTL implementation of algorithms for clock and data recovery, adaptive digital control, and DSP
* Communication with the architecture team to understand proposed algorithms and provide feedback regarding design implementation
* Digital design verification to ensure basic design functionality prior to hand-off of the design to the verification team
* Design verification using standard industry tools for HDL checking, e.g., CDC, RDC, Lint
* Support of the verification team in the debug of identified issues
* Assist with silicon bring up and debug
* Creation of clear design specifications and implementation documentation
Requirements
1. Extensive experience in RTL design methodologies, specification development, and design implementation
2. Familiarity with RTL design using a HDL such as Verilog or VHDL, with Verilog being a preference
3. Experience in modern digital ASIC methodologies including verification, STA, and signal integrity, DFT, synthesis, physical implementation
4.