Senior Verification Engineer Opportunity
At our company, we are seeking a seasoned Senior Verification Engineer to collaborate with architecture, design, physical implementation and software teams.
1. To ensure systems perform at the highest level, high-level modeling, UVM, HW/SW co-debug, and simulation acceleration support is essential.
2. The role involves reading and analyzing system requirements and architecture requirement documents.
3. We are looking for someone to develop detailed test and coverage plans based on architecture and micro-architecture.
4. The ideal candidate will have experience in developing verification methodology, ensuring scalability and portability across environments.
5. This includes developing verification environment development and maintenance in SystemVerilog/UVM/SystemC/C++, including stimulus, checkers, assertions, trackers, and coverage.
6. The successful candidate will execute verification plans, including design bring-up, DV environment bring-up, regression, and debug of test failures.
7. Using standard verification tools and workflows (simulators, coverage analyzers, Unix, CI, bug tracking) is crucial.
8. The individual will create and execute test cases to verify functionality, performance, and robustness in embedded C and SV.
9. We require someone who can identify, isolate, and debug verification issues, driving resolution with design and architecture teams.
10. Cross-functional team coordination to achieve verification closure, conducting coverage analysis, bug tracking, and regression testing is necessary.
11. Work organization and deliverables across teams, as well as mentoring and training junior verification engineers and coordinating functional verification teams, are key responsibilities.