Job Description
We are seeking a skilled Senior DFT Engineer to join our team. The ideal candidate will have a strong background in digital design and test engineering, with experience in designing, implementing, and validating test solutions for complex SoCs.
The successful candidate will collaborate with a talented team of engineers across Europe to work on cutting-edge architectures, improve silicon testability, and make a real impact in a fast-moving startup environment.
Key Responsibilities:
* Implement scan insertion, ATPG, Memory BIST, JTAG/IJTAG, and fault simulation flows.
* Collaborate with RTL, verification, and physical design teams to integrate DFT solutions efficiently.
* Support silicon bring-up and debug, helping to optimize test coverage and yield.
* Contribute to methodology improvements and share best practices with team members.
Requirements
To be considered for this position, candidates should have:
* Minimum 5 years of experience in DFT engineering, preferably on complex SoC projects.
* Experience with System Verilog RTL, TCL, Python, and Unix/Linux workflows.
* Core knowledge of hierarchical scan, ATPG, Memory BIST, JTAG/IJTAG, fault simulation, silicon debug, and gate-level verification.
* Experience with Siemens, Synopsys, or Cadence DFT tools.
* Bonus: Familiarity with IEEE 1149.x / 1500 / 1687 standards, synthesis flow, and timing analysis.
Benefits
As a member of our team, you can expect:
* An attractive compensation package.
* Extensive employee insurance.
* The option to receive company shares.
* A collaborative and inclusive work environment that supports creativity and innovation.
Location
Our offices are located in various European cities, including Leuven, Belgium; Amsterdam and Eindhoven, Netherlands; Zurich, Switzerland; Florence and Milan, Italy; and Bristol, UK.
Candidates based in these locations will have the opportunity to work from one of our offices, while others can work remotely from any European country.
Priority will be given to candidates who are based in Belgium or Italy.