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Lead Application Engineer
Apply locations CORK 01 time type Full time posted on Posted Today job requisition id R50571
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.
Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Title: Lead Application Engineer
Location: Cork
Reports to: AE Architect
Job Responsibilities:
* Help the customers in the increase of productivity, debug complex issues and provide solutions in the implementation of their Design and Verification flows.
* Working closely with R&D and Engineering to identify and prioritize the product improvement initiatives through formal methods and help in the customer adoption.
* Consult and understand the innovative design needs from customers and communicate with internal teams
* Creating high impact knowledge article content, tool adoption kits and other high-level documents to increase the self-help of customers
* Establish technical credibility and rapport with the customer and become the go-to expert for all their technical inquiries and support
* Champion the customer needs and work closely with R&D and marketing to develop competitive and creative technical solutions
* Assume technical leadership roles in small teams as needed.
Job Qualifications:
* BE/BTech/ME/MS/MTech in Electrical/Electronic Engineering or related field
* hands-on experience with design and verification/EDA indu
Requirements and Technical Skills
Minimum:
* Strong RTL and Testbench debug skills
* Strong HDL Design and Verification skills
* Experience with SystemVerilog, VHDL, Verilog
* Ability to quickly analyze verification environments and design complexity
* Strong verbal and written communication skills
* Ability to interact effectively with both external customers and R&D teams
Preferred:
* Familiarity with Code and Functional coverage
* Familiarity with Low Power Verification
* Familiarity with Gate level simulation
* Familiarity with Formal Verification
* Familiarity with C / C++ / SystemC, UVM
* Familiarity with scripting languages (Perl, Python or Tcl)
Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
Travel: If applicable, include an estimate of travel (e.g., “>10% domestic travel”).
We’re doing work that matters. Help us solve what others can’t.
Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.
Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.
Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
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