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Team Lead & Sr Principal Consultant | Semiconductor, Embedded Systems, CPU, GPU
UVM Design Verification Engineer
Working with a globally leading Semiconductor company working on cutting edge ASIC's, SoC and IP's.
Responsibilities:
* Perform verification planning
* Responsibility for the development of the verification environment from scratch using UVM.
* Responsibility for the functional verification and code coverage
* Defining and implementing test cases
* Regression debug support, and other flow/infrastructure development
* Implement verification of ASICs / IC'S / SoC's
Skills:
* SystemC / C/C++ is a plus
* Good knowledge of scripting language such as Python, CSH, Make
#verification #UVM
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Seniority level
* Seniority level
Mid-Senior level
Employment type
* Employment type
Full-time
Job function
* Job function
Engineering, Design, and Research
* Industries
Semiconductor Manufacturing, Computer Hardware Manufacturing, and Appliances, Electrical, and Electronics Manufacturing
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