Mixed Signal Design Verification Engineer
Salary: Very Attractive Rate
Location: N/A
Mixed-Signal Design and Verification Engineer Position Overview: We are seeking a talented and motivated Mixed-Signal Design and Verification Engineer to join our IC development team.
The successful candidate will be responsible for the design, modeling, and verification of analog and mixed-signal IPs integrated into complex SoCs.
This role involves hands-on transistor-level design as well as behavioral modeling and mixed-signal verification using state-of-the-art EDA tools and methodologies.
Key Responsibilities
Design and simulate analog and mixed-signal circuits such as ADCs, DACs, PLLs, bandgaps, amplifiers, LDOs, and sensor interfaces.
Perform schematic entry, transistor-level simulation, and layout supervision using Cadence Virtuoso or equivalent design environments.
Develop behavioral models (Verilog-A, Verilog-AMS, or real-number models) for system-level simulations and verification.
Conduct PVT and Monte Carlo analysis to ensure circuit robustness and yield.
Collaborate with layout engineers to optimize performance, area, and reliability.
Verification
Develop and execute mixed-signal verification environments integrating analog and digital domains.
Create SystemVerilog/UVM or Verilog-AMS testbenches for block-level and top-level verification.
Perform co-simulation using AMS tools (e.g., Cadence AMS Designer, Synopsys VCS AMS, Mentor Questa ADMS).
Develop and maintain real-number models (RNMs) to accelerate full-chip verification.
Define verification plans coverage metrics, and automated regression flows.
Debug simulation results and correlate design behavior across schematic, behavioral, and silicon domains.
Collaboration
Work closely with system architects, digital design, and validation teams to define specifications and interface requirements.
Support post-silicon validation, measurement correlation, and root-cause analysis of issues.
Document design methodologies, results, and best practices for reuse across projects.
Required Qualifications
Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field.
3+ years of experience in analog/mixed-signal circuit design and verification.
Strong proficiency in Cadence Virtuoso, Spectre, or similar SPICE-based tools.
Experience with SystemVerilog/UVM, Verilog-AMS, or real-number modeling.
Solid understanding of analog and digital fundamentals, including sampling theory, noise, linearity, and timing analysis.
Proficiency in scripting (Python, Perl, TCL) for simulation automation and data processing.
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