Overview
We are currently partnered with a leading semiconductor organisation developing cutting-edge GPU architectures. As part of their graphics engineering group, they are looking to hire a Staff CAD Engineer to drive methodology development and optimisation across the full ASIC design flow, with a focus on improving power, performance, and area.
This role is full time on-site.
Key responsibilities
Develop and deploy advanced CAD flows, methodologies, and algorithms to optimise PPA for GPU cores
Collaborate with graphics microarchitecture, RTL design, and physical implementation teams across the full design lifecycle
Drive improvements across the RTL-to-GDS flow, including synthesis, timing, power, and physical design
Identify bottlenecks and inefficiencies in design flows and implement scalable improvements
Key requirements
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
5–7+ years of experience developing CAD methodologies or flows focused on PPA optimisation
Solid understanding of ASIC design flow from RTL to GDS (synthesis, STA, physical design, verification)
Hands-on experience with industry-standard EDA tools (e.g., Synopsys Fusion Compiler, PrimeTime, PrimePower, RTL Architect)
Keywords:
CAD Engineering / GPU / ASIC / RTL-to-GDS / PPA Optimization / Synthesis / Static Timing Analysis / Physical Design / Formal Verification / ECO / Clock Tree / Synopsys / PrimeTime / Fusion Compiler / RTL Architect / Power Optimization / Semiconductor / Automation / Python / Tcl / Verilog
#J-18808-Ljbffr