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* We are looking for candidate who can code Pegasus DRC/LVS runsets based on given design rules document or given spec from customers or foundry partners. Develop automation to run regressions, auto detect issues and generate validation reports
* You are also expected to file bug reports and work closely with R&D team.
* Support customers on tool bugs, developments/improvements to enhance performance, add functionality and improve capacity
Qualifications
* BS degree with 1+ years of experience or MS degree in electrical engineering, computer science or equivalent.
Experience and Technical Skills required
* Experience in Developing Calibre/ICV/Assura/Pegasus runsets (DRC, LVS, Antenna) and validating testcases.
* Experience in DRC/LVS debugging for advanced nodes.
* Familiar with Chip fabrication process and 3DIC chip integration.
* Fluent in at least one of the following : TCL, Python, Unix-Linux platforms
* Must possess strong written, verbal and presentation skills
* Ability to establish a close working relationship with peers and management
* Explore what’s possible to get the job done, including creative use of unconventional solutions
* Work effectively across functions and geographies
* Push to raise the bar while always operating with integrity
Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
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