Company: ASICS Engineering
About the role
Qualcomm's Ser Des PHY team is seeking Analog / Mixed‑Signal design engineers to join our growing team in Cork, Ireland.
The successful candidate will work on analog and mixed‑signal integrated circuits for high speed PHY receivers and drivers, VCOs, PLLs, and a range of other custom IP for Qualcomm Mobile, Auto, Io T & Compute So C products.
The primary focus of the work is on low‑power and low‑voltage mixed‑signal design with emphasis on advanced nanometer Fin FET and GAA technology nodes.
The successful candidate will both design key circuit blocks and work closely with layout engineers to ensure the layout is fully optimised and complies with best analog layout practices.
You will be directly involved in delivering next‑generation Ser Des and PLL designs for Qualcomm So Cs and will be part of a large analog mixed‑signal design team involved in architecture analysis and IP delivery in leading‑edge Fin FET and GAA process technology nodes at 3nm and below.
The role requires industry experience in transistor‑level circuit implementations or highly relevant academic experience in a Masters' or Ph D program focused on full custom analog circuit design using nanometer CMOS technologies.
In addition to Analog and Mixed‑Signal circuit design expertise, good understanding of device physics, analog circuit custom layout, power distribution networks (PDN), mixed‑signal design flow, So C top‑level integration and IC Design Tools are desired.
Responsibilities:
Architecture, design, and development of analog / mixed‑signal hard macros for the Ser Des IP Design team
Perform custom circuit design in the latest Fin FET CMOS process technologies and beyond to support the delivery of Ser Des IP
Participate in internal customer requirements discussions
Create design specifications
Create behavioural models in Verilog
Set‑up, run and analyse circuit simulations
Perform quality assurance procedures on developed hard macros
Deliver hard macros and support customer integration and testing
Perform silicon characterization analysis and prepare silicon verification reports
Skills and Experience we would love to see:
Master's or Ph.
D.
degree in Science, Engineering, or related field
A minimum of 3‑years of transistor‑level analog mixed‑signal design experience, preferably in high‑speed wireline Ser Des, PLL, DDR or other high‑speed applications
Experience in SPICE simulators and schematic capture tools
Experience in designing op‑amps, bandgaps, differential amplifiers, VCO, PLL, DLL
Experience in high‑speed Ser Des block‑level designs such as transmitters, receivers, high‑speed VGA, CTLE, CDR, etc.
Understanding of signal integrity in high‑speed wireline design is preferred
Scripting to automate circuit design and verification work
Full‑custom analog layout techniques and the ability to complete layout extraction verification and sign‑off
Excellent communication skills and ability to contribute strongly within a high‑performance team
Minimum Qualifications:
Bachelor's degree in Science, Engineering, or related field
2+ years ASIC design, verification, or related work experience
Qualcomm is an equal‑opportunity employer.
If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process.
Please contact disability‑accomodations@qualcomm.com.
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