STA Design Engineer - ASIC / Low Power
We are partnered with a
global leader in semiconductors and wireless technology
focused on developing high-performance, low-power ASIC solutions for advanced cores and SOCs (System-on-Chips). The team are looking to hire an STA Engineer to take responsibility for conducting complex timing signoff activities and drive closure for next-generation products.
This is a permanent working opportunity based in Cork, Ireland.
Key responsibilities for this STA Design Engineer position:
* Perform Static Timing Analysis (STA) and drive timing closure for complex cores and full-chip SOCs (e.g., in the Snapdragon family).
* Evaluate block-level and top-level timing on gate-level PNR netlists.
* Provide critical feedback to the RTL, Synthesis, and Physical Design teams to improve Power, Performance, and Area (PPA).
* Create and execute Timing Engineering Change Orders (ECOs) to resolve critical timing violations.
* Enhance techniques and methodologies for timing closure and STA flow accuracy to reduce turnaround time (TAT).
* Develop automation scripts (Python, TCL, or Perl) for timing/power data mining and processing.
Key requirements:
* 4+ years of related work experience in Static Timing Analysis.
* Expert proficiency in STA tools such as PrimeTime, PrimeShield, or Tempus for hierarchical analysis in large SoCs.
* Hands-on experience with ECO tools (e.g., Tweaker, PrimeClosure, PTECO, Tempus ECO) for timing closure.
* Highly proficient in automation scripting using Python, TCL, or Perl.
* Strong knowledge of the complete ASIC design flow (RTL-to-GDS).
Keywords:
STA Design Engineer / Static Timing Analysis / STA / Timing Closure / ASIC Design / SOC / PrimeTime / Tempus / Timing ECO / PPA Optimization / Gate-Level Netlist / Python / TCL / Physical Design / RTL / Synthesis / Semiconductor / High-Performance Cores
If you are interested in this STA Design Engineer position, please send a CV to
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