Cpl are partnering with a market leading semiconductor organisation to appoint an experienced Principal Verification Engineer. This is a senior technical role within a high‑performing IP development team, focused on the verification of advanced DDR memory controllers used in next‑generation systems across datacenter, AI, automotive, and edge computing markets.
The Role
The successful candidate will take ownership of verification architecture and execution for complex controller IP, contributing at both a hands‑on and strategic level.
Key Responsibilities
Architecture and development of verification environments for complex IP
Design and implementation of UVM‑SV scoreboards and self‑checking testbenches
Creation of functional coverage models within metric‑driven verification frameworks
Development of SystemVerilog Assertions (SVAs) for simulation and formal verification
Definition and management of verification plans (vPlans) using industry‑standard tools
Setup and maintenance of automated regression flows (e.g. Jenkins)
Participation in technical reviews, checklist reviews, and formal quality processes
Close collaboration with design engineers to debug and resolve complex issues
Candidate Profile
Degree in Electrical / Electronic Engineering, Microelectronics, or a related field
10–15 years’ experience in the semiconductor, microelectronics, or EDA industry
Strong background in Verilog RTL design
Proven expertise in Metric Driven Verification (MDV)
Excellent communication skills and the ability to operate at a senior technical level
Self‑driven, organised, and comfortable working in globally distributed teams
What’s on Offer
Competitive salary and benefits package
Flexible working arrangements and multiple Irish locations
Opportunity to work on market‑leading IP used in high‑volume, mission‑critical products
Long‑term career progression within a technically strong organisation
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