As a Staff Digital Design Engineer, you will play a crucial role in shaping the future of mixed-signal ICs. We are looking for a skilled engineer to join our team and contribute to the development of innovative digital designs.
Job Overview
The successful candidate will be responsible for designing and implementing algorithms for clock and data recovery, adaptive digital control, and DSP. They will work closely with the architecture team to understand proposed algorithms and provide feedback regarding design implementation.
Key responsibilities include:
* RTL implementation of algorithms for clock and data recovery, adaptive digital control, and DSP.
* Communication with the architecture team to understand proposed algorithms and provide feedback regarding design implementation.
* Digital design verification to ensure basic design functionality prior to hand-off of the design to the verification team.
* Design verification using standard industry tools for HDL checking, such as CDC, RDC, and Lint.
* Support of the verification team in debug of identified issues.
* Assist with silicon bring up and debug.
* Creation of clear design specifications and implementation documentation.
Requirements
To be considered for this role, you should have extensive experience in RTL design methodologies, specification development, and design implementation. Familiarity with RTL design using a HDL such as Verilog or VHDL is required, with Verilog being a preference. Experience in modern digital ASIC methodologies, including verification, STA, signal integrity, DFT, synthesis, and physical implementation, is also essential.