Job Overview:
This role involves leading the physical implementation of next-generation high-speed System-on-Chip (SoCs), pushing Performance, Power, and Area (PPA) limits in advanced technologies such as 7nm and 5nm.
* Floorplanning
* Power optimization
* Timing closure
Responsibilities:
* Own the full physical design flow from netlist to GDS.
* Develop new methodologies to boost performance, power, and area efficiency.
* Collaborate with timing, power, and verification teams to tackle complex PPA challenges.
Requirements:
* At least 4 years of experience in Physical Design.
* Solid knowledge of the entire PD flow.
* Hands-on experience with physical design tools for advanced technology nodes (10nm and below).
Key Skills:
* Expertise in floorplanning and placement.
* Proficiency in power optimization techniques.
* Strong understanding of timing closure methods.
What We Offer:
A competitive salary and benefits package, opportunities for career growth and professional development, and a collaborative work environment that fosters innovation and creativity.