General Summary
Qualcomm’s Mixed‑Signal IP (MSIP) Design Verification team is seeking Mixed‑Signal Design Verification Engineers to join our team in Cork, Ireland. The Qualcomm Cork site is home to a range of MSIP teams working on cutting‑edge designs for the latest Snapdragon SoCs in the latest technology nodes, and the successful candidate will work on mixed‑signal verification for several key mixed‑signal PHY IPs including DDR, USB, PCIE, eDP, DPRX, HDMI, SGMII, DSI, CSI, PLL IP and more. The Design Verification team in Cork uses the latest tools and verification techniques in leading‑edge silicon nodes at 3 nm and below, and team members work directly with architecture, design, software and SoC teams in Ireland and other global Qualcomm locations.
Responsibilities
SV/UVM based Design Verification of SerDes, DDR & PLL Mixed‑Signal PHY IP
Emulation experience is desired along with SV/UVM based simulation
Work closely with analog and digital front‑end design teams to verify RTL and analog/mixed‑signal designs in next‑generation SerDes, DDR & PLL IP
Interact with architecture, design, physical design, software, test and SoC teams to verify and integrate SerDes, DDR & PLL IP designs into the latest Qualcomm Snapdragon products
Skills and Experience
Bachelor’s degree in Engineering, Computer Science or related field
Experience in design and verification of hardware and software on SoCs and SoC/IP methodologies for verifying complex units using industry standard tools
Knowledge in developing unit and SoC/IP level test benches using UVM
Constrained random functional verification environment in SystemVerilog/UVM with excellent debugging skills
Experience in low power verification using UPF at RTL and GLS simulation level
Experience in power‑aware gate‑level simulation (GLS) verification flow with zero‑delay and SDF‑annotated simulation
Experience of pre‑ and post‑silicon verification testflow and automated test benches; post‑silicon ATE/PTE vector bring‑up and bench characterization support
Knowledge of test‑plan development, coverage (code/functional) analysis, transaction‑level modelling, constrained random verification, assertion‑based and formal verification techniques with SystemVerilog
Experience with Verilog, SystemVerilog, Assertions, Python/TCL/Perl/shell‑scripting
Experience with analog mixed‑signal verification techniques is a plus
Excellent communication skills
Minimum Qualifications
Bachelor’s degree in Science, Engineering or related field
2+ years design verification or related work experience
Equal Opportunities
We are an equal‑opportunity employer; all qualified applicants will receive consideration for employment without regard to race, colour, religion, sexual orientation, gender identity, national origin, disability, veteran status or any protected classification.
Benefits
Salary, stock and performance‑related bonus
Maternity/Paternity leave
Employee stock purchase scheme
Matching pension scheme
Education assistance
Relocation and immigration support (if needed)
Life, medical, income and travel insurance
Subsidised memberships for physical and mental well‑being
Bicycle purchase scheme
Employee run clubs, including running, football, chess, badminton and many more
Location
Cork has a proud reputation as Ireland’s second largest economic engine and is one of the top 20 location choices in Europe. It offers excellent quality of life and a gateway to Europe, with Cork Airport providing access to many international destinations.
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