Role Overview
We are seeking a senior Digital Design Member of Technical Staff (MTS) to lead and deliver digital controller IP for power, clock, and error management subsystems within the onsemi Treo™ platform. This hands‑on technical leadership position focuses on architecting, designing, integrating, and evolving complex digital IP that tightly interfaces with analog and mixed‑signal blocks in automotive‑grade SoCs.
Successful candidate brings deep experience in automotive functional safety, digital‑analog co‑design, and system‑level integration, while serving as a technical mentor and thought leader within the Cork design organization.
Responsibilities
Architect, design, and implement digital system controllers for power management, clock management, and error detection, reporting, and mitigation subsystems.
Develop robust digital IP that controls and interacts closely with analog and mixed‑signal blocks.
Own IP delivery from architecture through RTL, verification, integration, and silicon bring‑up support.
Drive and support digital‑on‑top product integration flows, including integration into SoC environments, clocking, reset, power domain, and safety integration.
Ensure designs meet automotive functional safety requirements (ISO 26262 concepts such as ASIL, fault coverage, diagnostic mechanisms).
Collaborate cross‑functionally with analog design, verification, physical design, systems, safety, and product engineering teams.
Define and evolve IP roadmaps aligned with platform strategy, product requirements, and long‑term business objectives.
Mentor and technically guide junior and mid‑level engineers, promoting best practices in design, documentation, and review culture.
Contribute to continuous improvement of design methodologies, verification strategies, automation, and productivity tools.
Stay technically curious and engaged with emerging AI/ML applications in digital design, including their potential impact on RTL development, verification, and productivity.
Required Qualifications
15+ years of hands‑on digital design experience, primarily in ASIC or SoC development.
Proven experience delivering automotive IP with functional safety requirements.
Strong background designing digital controllers for analog blocks (power regulators, PLLs, sensors, clocking systems).
Deep understanding of system‑level digital integration, including power and clock domain management, reset strategies, error handling and safety mechanisms.
Solid experience with RTL design (SystemVerilog).
Working knowledge of constrained‑random verification methodologies, including SystemVerilog and UVM.
Demonstrated ability to work effectively as a senior individual contributor, owning complex technical problems end to end.
Strong communication skills and a demonstrated willingness to mentor junior engineers.
Preferred / Plus Qualifications
Experience with automotive safety standards such as ISO 26262 (concept, system, or IP‑level application).
Working knowledge of JIRA for task tracking and JAMA for requirements management.
Exposure to safety diagnostics, fault injection, or safety verification techniques.
Experience contributing to platform‑level IP strategies or multi‑generation roadmap planning.
Familiarity with low‑power design techniques and power‑aware verification.
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