A Global semiconductor giant based in Cork are seeking to bolster their team with a talented Sensor Design Verification Engineer.
Responsibilities
Develop and execute advanced verification strategies using methodologies such as UVM and formal verification.
Build and maintain verification environments, including testbenches, reusable components (UVCs), and C-based models.
Verify RTL implementations of sensor algorithms to ensure readiness for ASIC tapeout, including debugging and optimisation.
Create and manage test plans, analyse coverage results, and collaborate with design teams to resolve gaps and issues.
Support system integration and team efficiency through regression management, Python automation, documentation, and cross-team debugging.
Key Requirements
Master’s degree in Engineering, Science, or a related discipline.
Minimum of 6 years’ experience in ASIC design verification or UVM-based functional verification.
Strong expertise in SystemVerilog, UVM, assertions, and RTL simulation tools, with scripting skills (Python/Perl).
Experience with constrained-random and coverage-driven verification methodologies, including debugging and coverage analysis.
Excellent analytical, communication, and teamwork skills, with the ability to thrive in a fast-paced environment.
If this role is of interest please apply directly on LinkedIn or send a copy of your CV to alex@eu-recruit.com.
By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice (https://eu-recruit.com/about-us/privacy-notice/)
#J-18808-Ljbffr