Social network engineer sought to design and develop high-quality analog/RF systems and sub-systems.
Key Responsibilities
* Create complex Analog/RF systems/sub-systems using industry best practices for design, verification, and testing according to project plans.
* Develop, document, and verify behavioural models of analogue and analogue-mixed-signal blocks (e.g. using VerilogA/AMS, SystemVerilog-RNM, Wreal) ensuring they are optimised and up-to-date.
* Design and implement automated test benches and verification plans.
* Design and verify RF/Analog blocks/subsystems (e.g. LNA, PA, VCO, PLL, mixers, bandgaps, LDO, DC-DC, ADC, DAC, etc) operating up to 20GHz frequency range using industry-standard tools and design flows.
* Collaborate with IC Layout Design Engineers to optimize design and layout.
* E nsure that designs adhere to industry best practice design flows, verification techniques, Design For Test (DFT), isolation, power optimization, etc.
* Support lab evaluation, characterization, and testing.
Interpersonal Skills
* Communicate effectively with mixed signal, digital/systems/SW/apps/test teams to ensure products meet specifications on time and in budget.
* Foster a team-oriented environment with good interpersonal skills and ability to work independently on complex tasks.
* Promote continuous productivity improvements through improved work methodologies, efficient tool use, and good documentation.
* Mentor junior employees and interns.
Qualifications
* Bachelor or Master of Science degree in Electronic Engineering or related field required.
* A minimum of 10 years relevant industrial experience is necessary.
* Proficiency in Cadence Virtuoso design environment is essential.
* Detailed experience designing analog/mixed-signal circuits on advanced CMOS nodes (40nm and lower) is required.
* Clear and concise communication and presentation skills are necessary.
* Experience with getting full chip designs to product release preferred.
* Knowledge of high-frequency RF designs is highly desirable.